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EMD02N10TL8 Datasheet

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Excelliance MOS · EMD02N10TL8 File Size : 625.60KB · 7 hits

Features and Benefits

-to-Ambient3 RθJA 1Pulse width limited by maximum junction temperature. 2Duty cycle < 1% 342°C / W when mounted on a 1 in2 pad of 2 oz copper. 4Guarantee by Engineering test EMD02N10TL8 LIMITS ±20 304 192 29 23 761 88 387.2 193.6 313 125 3 1.9 -55 to 150 UNIT V A mJ W W °C MAXIMUM 0.4 42 U.

EMD02N10TL8 EMD02N10TL8 EMD02N10TL8
TAGS
Single
N-Channel
Logic
Level
Enhancement
Mode
Field
Effect
Transistor
EMD02N10TL8
EMD02N06E
EMD02N06TL8
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